1999-01-17  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* ANNOUNCE: added.

Sun Jan 17 11:24:43 EST 1999  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a3 to 1b0.

1999-01-13  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-and): added.  Turn (and a ... z) into
	(if (&& a ...) z 0).

1999-01-12  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* Makefile (version.txi): support added.

	* synch.texi (SIMSYNCH_VERSION): abstracted to version.txi.

1999-01-08  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): translate booleans as 0 and 1.

	* simsynch.scm (create-board): removed constants `f' and `t'.

	* scm2vrlg.scm (negate-result?): removed; instead pass polarity
	argument to translate-assignment.

1998-12-16  Radey Shouman  <Radey_Shouman@splashtech.com>

	* scm2vrlg.scm (instantiate): Added comma output where necessary.
	
1998-12-15  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* simsynch.scm (dump:spew): dump stuff simplified.

1998-12-15  Radey Shouman  <Radey_Shouman@splashtech.com>

	* simsynch.scm (synch:dump-vector): (synch:dump-scalar): Added
	functions for writing Verilog compatible dump files.
	
1998-12-15  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (instantiate): Now takes separate signal group
	argument; print nice comments.
	(generate-module-header): Now pretty-prints scheme code for
	dumping module state.
	(merge-bounds): Now keeps track of pin names associated with
	merged signal.

1998-12-14  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (call-with-classified-pins): only imports/exports
	pins and signals used by other blocks.

	* simsynch.scm (used-in-table mark-uses used-by-other-blocks?):
	Created to keep track of which signals are used in which blocks.

1998-12-11  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): include "logical.v" from each
	non-trivial module.
	(call-with-classified-pins): classify internal signals as
	input and output if within block.
	(translate-tag): create declarations of macros (wire) before
	assign statements.

1998-12-10  Aubrey Jaffer  <jaffer@ai.mit.edu>

	* scm2vrlg.scm (translate-tag): Now generates separate modules for
	each block within a ptag.
	(translate-text-macros): removed; macros now generate assign =
	statements.
	(out-bufs out-buf): removed (already commented out).
	(generate-module-header): don't generate constants for trivial modules.
	(instantiate): used for both `module' statements and instantiations.

1998-11-10  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-exp): shift direction was backwards.

1998-11-09  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): self-setting signals reset
	removed.

	* scm2vrlg.scm (translate-tag): outputs conditional assignments
	(with ..'bz) rather than bufif1 statements.

	* scm2vrlg.scm (translate-assignment): Restored self sets.  =
	changed to <= for assignments.

1998-10-07  Aubrey Jaffer  <aubrey_jaffer@splashtech.com>

	* scm2vrlg.scm (translate-tag): fixed self-initing/input register
	reset generation.

Sat Aug 8 22:57:38 EDT 1998  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a2 to 1a3.

1998-07-21  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (ptag-stripped): return #f for 'tag: argument.
	(ptag-stripped): return number if stripped pin-name is.

	* simsynch.scm: pin-number and pin-num renamed to pin-name and
	pin-nam.  PTAG can now be specified on pin-nam.  Pin-nams can be
	vectorized (dq[32..00]).

	* logic.scm (ptag-stripped): 
	(ptag-prefix): now pass numbers.

	* simsynch.scm (synch:define): now takes optional NEXT-FUNCTION
	argument.

1998-07-20  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (translate-assignment): elides self-sets.

	* models.scm (synch:fifo): no longer generates external names.
	All are passed as arguments.
	* logic.scm (array-bounds): puts out nicer looking index
	calculations.

1998-07-17  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (symbol-append): beefed up to tolerate strings and numbers.

	* scm2vrlg.scm: Added array support.

	* models.scm (synch:fifo): added macro to instatiate FIFO memory.

1998-07-17  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm (signal-table:get-init-fun): added.

	* logic.scm (array-bounds): added.

	* scm2vrlg.scm (translate-tag): moved call to
	translate-text-macros before generate-module-header.
	(call-with-classified-pins): now knows about arrays.

1998-07-16  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (translate-exp): ash of negative numbers now uses
	`>>'.

	* synch.texi (Models): Added chapter.

	* simsynch.scm (pld): added ORCA3 package types.
	(synch:define-bus): Doesn't count #t enabled drivers -- these are used
	to model pullup/down.

	* scm2vrlg.scm (translate-exp): added `+' and `-'.

	* models.scm (make-ram-array): added.

1998-07-15  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm (make-ram): added.

1998-06-11  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (booleans-to-number): commented out warning.

	* simsynch.scm: Added CHECK-TURNAROUND feature.  This enables
	checks generated by synch:define-bus.

1998-06-08  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm (out-decl merge-bounds call-with-classified-pins):
	split out from generate-verilog-header.
	(generate-stimulus): now instantiates module with symbols.  primitive
	initial assignments added.

1998-05-29  Aubrey Jaffer  <jaffer@colorage.com>

	* Makefile (expander.scm): removed.

	* simsynch.scm (synch:set!): multiple synch:set!s now COMPOSE-SETS
	of new-states.

	* models.scm (make-fifo): added optional width-prototype field.

1998-05-26  Radey Shouman  <radey@colorage.com>

	* run.scm: Added error message for unknown translate target.

	* scm2vrlg.scm: Added support for BITWISE-IF.

1998-05-26  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm, scm2mach.scm: Added BIT-FIELD as alias for BIT-EXTRACT.

	* Makefile: split html target into html and cvshtml.

	* synch.texi: Included and reordered documentation for new
	(SLIB/SCM) logical operations.

	* simsynch.scm (define-synchronous-system): fixed
	(<block-name> <signal>) to work during reset.

1998-05-22  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm, scm2vrlg.scm, scm2mach.scm:
	(<block-name> <signal>) now retrieves value.

	* scm2vrlg.scm, simsynch.scm, scm2mach.scm:
	SYNCH:PRE no longer requires (nor works with) #.

	* Makefile: models was missing from distribution.

1998-05-21  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm: Includes "models.scm".

1998-05-20  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm: changed make-uniform-array prototype to #xffffffff.

Thu May 21 22:03:34 EDT 1998  Aubrey Jaffer  <jaffer@aubrey.jaffer>

	* Makefile (VERSION): Bumped from 1a1 to 1a2.

1998-05-20  Aubrey Jaffer  <jaffer@colorage.com>

	* models.scm: changed make-uniform-array prototype to #xffffffff.

1998-05-19  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm: fixed compose-sets

	* models.scm: fifo:clear added.

	* scm2vrlg.scm: Made NOT ifable.

	* scm2vrlg.scm: Added case-eval; no longer substitute values for
	constants in CASE statements.

	* scm2mach.scm: case-eval: no longer need to substitute values for
	constants in CASE statements.

	* scm2mach.scm: MACHXL string constant number must not have
	enclosing parentheses.

1998-05-14  Aubrey Jaffer  <jaffer@colorage.com>

	* scm2vrlg.scm: In symbol names : => _

	* simsynch.scm, scm2vrlg.scm, scm2mach.scm: Translators now handle
	defconst (and , in casev).

1998-05-13  Aubrey Jaffer  <jaffer@colorage.com>

	* simsynch.scm: CEVAL added; evals constant

	* scm2vrlg.scm: translate-= replaced using verilog ==

	* scm2mach.scm: Added CASEV support.

1998-05-12  Aubrey Jaffer  <jaffer@colorage.com>

	* synch.texi, scm2vrlg.scm, logic.scm: defconst definition made
	conditional; (scm now defines).  memocase -> casev

	* logic.scm, ChangeLog: logic.scm (memocase): Now case compatible
	with unquote or unquote-splicing in datum-list.

	* .cvsignore: added core

	* Makefile: A dummy directory (like core/) needs to be in the
	source dir in order to get a pane with the sequential log button
	in it. (cvs2html)

1998-05-12  radey  <radey@scm.colorage.net>

	* synch.texi: documentation for memocase

1998-05-12  Aubrey Jaffer  <jaffer@colorage.com>

	* logic.scm (memocase): Now case compatible with unquote or
	unquote-splicing in datum-list.

Thu Oct 30 10:38:54 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* logic.scm (count): count booleans added.

Wed Jun 11 16:01:27 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* simsynch.scm (define-synchronous-system): now keeps track of
	SYNCH:STATE explicitly.

Fri May 16 10:08:30 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* scm2mach.scm (compile-tops): headers now use coded time in time
	field.  CZ support added; slightly different format.

Thu Apr  3 17:17:11 1997  Aubrey Jaffer  <jaffer@martigny.ai.mit.edu>

	* run.scm (translate): generalized for use with DESIGN.
